An IC may include a memory array having a plurality of memory cells interconnected by bitlines in first (column) and wordlines in second (row) directions. The array can be organized in a plurality of memory blocks. During fabrication of the IC, one or more memory cells can be defective. To repair the defective cells, redundant memory cells are provided.
FIG. 1 shows a block 101 of redundant cells for repairing defective cells in the memory array. As shown, the block comprises a plurality of redundant elements 120a-h. A redundant element typically comprises a plurality of cells configured for row and/or column redundancy. Typically, the memory array is separated into memory elements corresponding to the redundant elements. When a defect occurs in a memory element, it is replaced with a redundant element. Each redundant element is associated with a fuse block 132 from a fuse bank 130. As used herein, a redundant element and associated fuse block is referred to as a “redundancy unit”. A fuse block includes a plurality of fuses to facilitate redundancy. The use of fuses to facilitate redundancy is described in, for example, Taylor et al., IEEE JSSC, Vol. SC-20, No. 5 (October, 1985), which is herein incorporated by reference for all purposes.
Conventionally, the fuses can be either laser or electrically blowable fuses. Laser type fuses are used to repair defects prior to packaging. For example, after the IC is fabricated, the IC is tested at the wafer level (i.e., prior to dicing). Defective cells are identified and repaired with redundant elements by blowing the fuses using a laser. An electrical type fuse, on the other hand, is blown by sending an electrical current which exceeds the capacity of the fuse, thereby blowing it. Electrical fuses are used to repair defective cells after the IC is packaged.
To provide repairs both before and after packaging both types of fuse blocks (e.g., laser and electrical) are provided, each associated with a redundant element. However, unused laser type redundant elements cannot be used after the IC is packaged. This results in an inefficient use of chip area, which increases manufacturing costs as well as chip size.
From the foregoing discussion, it is desirable to provide an improved redundancy scheme that reduce costs and chip size.